65C02 CPU in Atari, explanation of schematics.

First the easiest part, the extra PIA.
The PIA has a total of 3 Chip Select lines. The Atari only uses one, 
the pin 23 CS2 line which is active low. The other 2 are active high, 
pins 22 and 24 and are normally connected to VCC.
The PIA only uses four addresses but the MMU (Memory Management Unit) 
reserves 256 bytes in $D300 to $D3FF. To select an extra PIA, the 
A7 line is inverted by IC9, a 74LS04. The A7 line is connected to 
pin 9 of the inverter and comes out on pin 8. This inverted A7 is 
used to drive the "original" PIA pin 22, the CS0 line. The A7 line is 
used to drive the CS0 line of the extra PIA. The original PIA is now 
on $D300 to $D37F and the extra is on $D380 to $D3FF.
Note: When Using the second PIA U8 cut the Trace from the
Socket U7 Pin 22 to PIA U7 Pin 22.
(This can be done once more with the A6 line also. Pin 5 of U9 
inverter. The space is divided into four parts. D300 to D33F; D340 to 
D37F; D380 to D3BF and D3C0 to D3FF. The PIA Pin 24 should be used 
for this. Cut the trace connecting the PIA to the plug and connect 
the inverted A6 line to pin 24 for of the PIA's. All programs will 
work and the extra parts can be accessed at D340 to D37F and D3C0 to 
D3FF)

The RTC is an Oki MSM 5832.
It's connected to the PIA's port B. The source code makes clear how 
to use it and also explains how to write an Atari driver.

The other PIA port can be used to make a Centronics port to drive a 
printer. The data lines are buffered with a 74LS244 and the strobe 
and busy are buffered with the 74LS01 IC9.
See a data sheet on the 6520 or 6821 (Same chip) to find out how to 
program the PIA.

The next part is more difficult, the 65C02 Processor.
Both the original Atari 6502C and the C-Mos 65C02 have a limited 
drive capacity (Fan-out). This is one of the reasons for the buffers 
74F244 and 74F245. These buffers may also be 74LS or 74ALS. (74S is 
not tested but may also work)
The buffers may also be "Tri-stated" (Isolation between input and 
output) This is needed when the HALT line is activated by the ANTIC 
to signal the CPU that ANTIC wants the bus. Once HALT is active (low), 
the signal is latched by U2, half a 74LS74. The signal is latched on 
the Q1 clock going high. The inverted output of the latch goes to 
"high" and disables the buffers, the R/W line and the clock into the 
CPU. As the clock signal is stopped, the CPU "freezes" And it's a 
Static design, so there's no need for a clock signal to refresh 
registers. This feature was also build in the Atari 6502C Processor.
The last part is the generation of the Q1 and Q2 signal by the U2 
part 2. The LS02 port inverts the Q0 signal that was originally fed 
to the CPU. The Q0 and inverted Q0 drive the set and reset lines of 
the 74LS74 and this generates the non-overlapping clocks Q1 and Q2. 
(Not stopped by HALT as the processor signals would be) The timing 
is a bit critical here. Other 74 types may not work.

Note: To use a 65C816 at another clock speed, the input into the CPU 
should be changes and the 74LS74 left unchanged. This is being 
investigated.